Alif Semiconductor /AE512F80F5582LS_CM55_HE_View /OSPI0 /OSPI_RXFTLR

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Interpret as OSPI_RXFTLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RFT

Description

OSPI Receive FIFO Threshold Level Register

Fields

RFT

Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is 256. If the value in this bit field is greater than the depth of the FIFO, this bit field is not written and retains its current value. When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered.

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